The present invention relates generally to an exposure method, and more particularly to an optimization of an exposure condition of the exposure apparatus and an optimization of a reticle or mask pattern. The present invention is suitable, for example, for the optimizations of the exposure condition and reticle pattern to expose a pattern of a semiconductor memory.
A conventional projection exposure apparatus uses a projection optical system to expose a reticle pattern onto a wafer etc., and an exposure apparatus that provides exposure at a high resolution has been increasingly demanded. An optimization of the exposure condition and reticle pattern is important to increase the resolution. A reticle pattern is optimized, for example, by an optical proximity correction (“OPC”). For an effective optimization, use of a simulation or simulator is known. See, for example, Japanese Patent Applications, Publication Nos. 2002-319539, 2002-324752, 06-120119, 08-335552 and 2002-184688.
A semiconductor memory, such as a DRAM and an SRAM, includes a memory cell as a storage region in a RAM and its peripheral circuit. In general, the optimization of the exposure condition and the reticle pattern requires information on part of the pattern to be optimized and a target value of the part (such as a margin and a size) as well as information of the whole pattern. Thus, mere pattern information of a real device or chip would be insufficient for the optimization. Often, a lithography engineer does not know information on the peripheral circuit pattern, and hardly acquires the information of the entire pattern of the entire real device. In addition, numerous parts need to be optimized on the pattern of the whole real device, and the optimizations of all of these parts are time-consuming and impracticable. Thus, prior art optimizes the exposure condition and reticle pattern only for the memory cell pattern, not the entire real device, in exposing a semiconductor memory pattern. See, for example, Japanese Patent Application, Publication No. 2005-26701, D. Flagello et al., “Optical Lithography in the sub-50 nm Regime,” Proc. SPIE, vol. 5377 (2003).
However, the exposure condition and reticle pattern optimized only for the memory cell are likely to cause patterning failures for the peripheral circuit, and do not always improve the resolution of the whole chip on average.